Title :
A 622 Mbps ATM physical layer ASIC and its “design for test” methods
Author :
Kim, Chan ; Park, Yeong Ho ; Eom, Doo Sub ; Kim, Jae Keun
Abstract :
A 622 Mbps ATM physical layer ASIC design is described. This ASIC performs the full 622 Mbps ATM physical layer functions according to the ITU-T I.432 and ATM Forum UNI standards. The cells are processed at 77.76 MHz speed but most of the other STM related circuits run at te 19.44 MHz clock rate. Each functional block is explained with its robust synchronization mechanism among other processing blocks. The design aspects and techniques for the ASIC test are explained for scan test and additional functional test in a reduced frame mode which was specially designed for this ASIC. Most of the basic functions were verified through loop-back test including fiber loops
Keywords :
application specific integrated circuits; asynchronous transfer mode; design for testability; digital signal processing chips; synchronisation; telecommunication standards; 19.44 MHz; 622 Mbit/s; 77.76 MHz; ATM Forum UNI standards; ATM physical layer ASIC; ITU-T I.432 standard; STM; clock rate; design for test methods; fiber loops; functional test; loop-back test; processing blocks; reduced frame mode; synchronization mechanism; Application specific integrated circuits; Asynchronous transfer mode; Bandwidth; Circuit testing; Clocks; Containers; Design methodology; Frequency synchronization; Physical layer; Robustness;
Conference_Titel :
Computers and Communications, 1997. Proceedings., Second IEEE Symposium on
Conference_Location :
Alexandria
Print_ISBN :
0-8186-7852-6
DOI :
10.1109/ISCC.1997.616023
