• DocumentCode
    3421427
  • Title

    Modulo-free architecture for binary to residue transformation with respect to {2m-1, 2m, 2m+1} moduli set

  • Author

    Pourbigharaz, F. ; Yassine, H.M.

  • Author_Institution
    Dept. of Electr. Eng. & Electron., Brunel Univ., Uxbridge, UK
  • Volume
    2
  • fYear
    1994
  • fDate
    30 May-2 Jun 1994
  • Firstpage
    317
  • Abstract
    A binary to residue converter architecture based on the {2m -1, 2m, 2m+1} moduli set is presented. This is achieved by deriving a formula to compute the residue of an integer with respect to the modulus 2m+1. By replacing the end-around carry propagate stage with a simple multiplexer, the delay is reduced to O(m) adder delays. The proposed architecture is free of module adders
  • Keywords
    Added delay; Arithmetic; Computer architecture; Dynamic range; Electronic mail; Multiplexing; Out of order; Propagation delay; Signal processing; Zinc;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
  • Conference_Location
    London
  • Print_ISBN
    0-7803-1915-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1994.408968
  • Filename
    408968