Novel asymmetric 8T SRAM cell with dynamic power

Author

Yi-Nan Mo ; Guo-Qiang Hang ; Dan-Yan Zhang

Author_Institution

Sch. of Inf. & Electr. Eng., Zhejiang Univ. City Coll., Hangzhou, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

Data stability, power consumption and delay are important issues with the scaling of CMOS technology. An asymmetric eight-transistor SRAM cell with improved static-noise margin (SNM) is proposed. In this new 8T SRAM cell, unilateral reading mechanism and dynamic power scheme are combined. Results are validated by HSPICE simulation using 45nm PTM model. The simulated results of the SNM, the power consumption, the propagation delay and the power delay product (PDP) are compared between the dynamic power 6T SRAM cell and the proposed 8T SRAM cell.

Keywords

SRAM chips; circuit simulation; circuit stability; delay circuits; integrated circuit noise; transistors; 6T SRAM cell; 8T SRAM Cell; CMOS scaling technology; HSPICE simulation; PDP; PTM model; SNM; asymmetric eight-transistor SRAM cell; data stability; delay propagation; dynamic power scheme; improved static-noise margin; power consumption; power delay product; predictive technology model; size 45 nm; unilateral reading mechanism; Delay; Power demand; SRAM cells; Stability analysis; Transistors; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467901

Filename

6467901