A multithreaded multimedia processor merging on-chip multiprocessors and distributed vector pipelines

This paper introduces a new multimedia processor architecture that exploits all sorts of parallelism that can be found in multimedia applications, namely data, instruction, thread and transfer level parallelism. The proposed architecture issues simultaneously several scalar and vector threads on an array of functional units to mask pipeline stalls due to functional and memory units latencies or cache misses. The clustering of the architecture in several processors communicating through register channels and stream Buffer allows high clock frequency implementation and reduces the ever growing interconnection delay influence. Several motion estimation algorithms have already been implemented to show the efficiency of the architecture to adapt its resources allocation to better fulfil the application intrinsic vectorizing ratio