A transformation for computational latency reduction in turbo-MAP decoding

Author

Raghupathy, Arun ; Liu, K. J Ray

Author_Institution

Qualcomm Inc., San Diego, CA, USA

Volume

fYear

1999

fDate

36342

Firstpage

402

Abstract

The SOVA and the log-MAP are commonly used in turbo decoding. In this paper, we propose to modify the sliding window MAP-algorithm to reduce the computational delay even further. We compare the simulation performance of this low latency log-MAP algorithm with the sliding window log-MAP. We also estimate the VLSI implementation complexities of the SOVA, the log-MAP and the proposed low latency log-MAP

Keywords

VLSI; computational complexity; maximum likelihood decoding; turbo codes; AWGN channel; VLSI implementation complexities; computational latency reduction; fading channel; fast backward acquisition; low latency log-MAP algorithm; modified sliding window MAP-algorithm; reduced computational delay; simulation performance; soft output Viterbi algorithm; turbo-MAP decoding; AWGN channels; Computational modeling; Computer architecture; Delay; Fading; Iterative algorithms; Iterative decoding; Speech; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780027

Filename

780027

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=342209