Title :
Recursive maximum likelihood decoder for high-speed satellite communication
Author :
Miki, Morgan H. ; Taki, Daisuke ; Fujita, Gen ; Onoye, Takao ; Shirakawa, Isao ; Fujiwara, Toru ; Kasami, Tadao
Author_Institution :
Dept. of Inf. Syst. Eng., Osaka Univ., Japan
Abstract :
A decoder of (64,35) Reed-Muller subcode has been implemented, dedicatedly for high-speed satellite communication. The trellis-based recursive maximum likelihood decoding algorithm, which greatly reduces the computational costs of the conventional Viterbi algorithm, can be performed on a single chip by using 3-stage pipeline architecture of an add-compare-select (ACS) tree. By using 0.6 μm CMOS triple-metal technology, the (64,35) decoder integrates totally 160,023 gates into a 151.3 mm2 die and operates at 60 MHz. The 600 Mbps (64,40) decoding system required for satellite communication can be constructed by employing 32 proposed decoders in parallel
Keywords :
CMOS digital integrated circuits; Reed-Muller codes; VLSI; block codes; digital communication; digital signal processing chips; high-speed integrated circuits; linear codes; maximum likelihood decoding; parallel architectures; pipeline processing; satellite communication; trellis codes; (64,35) decoder; 0.6 micron; 60 MHz; 600 Mbit/s; CMOS triple-metal technology; Reed-Muller subcode; add-compare-select tree; high-speed satellite communication; linear block codes; parallel connected decoders; recursive maximum likelihood decoder; three-stage pipeline architecture; trellis-based recursive ML decoding algorithm; Binary phase shift keying; Block codes; Error correction codes; Information systems; Maximum likelihood decoding; NASA; Pipelines; Satellite communication; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780069
