DocumentCode :
3422865
Title :
A fine pitch and high aspect ratio bump fabrication process for flip-chip interconnection
Author :
Yamada, Hiroshi ; Saito, Masayuki
Author_Institution :
Labs. of Mater. & Devices, Toshiba Corp., Yokohama, Japan
fYear :
1995
fDate :
4-6 Dec 1995
Firstpage :
121
Lastpage :
124
Abstract :
This paper describes the fabrication process for the finest pitch and highest aspect ratio bump arrays reported so far. Particularly noteworthy is the development of a new microstructural resist patterning technique in which electroplating is used to form the bumps. The alkaline solubility and dissolution effect parameter of the resist were evaluated to obtain the precise microstructural pattern. The finest pitch and highest aspect ratio resist patterns fabricated had a 10 μm pitch with a 5 μm diameter and a 50 μm height, and they were arranged 5 μm apart from each other
Keywords :
electroplating; fine-pitch technology; flip-chip devices; integrated circuit interconnections; resists; alkaline solubility; aspect ratio; bump array; dissolution; electroplating; fabrication; fine pitch process; flip-chip interconnection; microstructural resist patterning; Ceramics; Encapsulation; Fabrication; High-speed electronics; Laboratories; Large scale integration; Resins; Resists; Silicon; Thermal stresses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Manufacturing Technology Symposium, 1995, Proceedings of 1995 Japan International, 18th IEEE/CPMT International
Conference_Location :
Omiya
Print_ISBN :
0-7803-3622-4
Type :
conf
DOI :
10.1109/IEMT.1995.541008
Filename :
541008
Link To Document :
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