• DocumentCode
    3423387
  • Title

    Effect of wire bond and die layout on electrical performance of power packages

  • Author

    Yumin Liu ; Carredo, Mark Rembrandt T ; Hu, Zhiping ; Liu, Yong ; Luk, Timwah ; Irving, Scott

  • Author_Institution
    Fairchild Semicond., Suzhou
  • fYear
    2009
  • fDate
    26-29 April 2009
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    In power packages, the DC test for RDS(ON), AC test for various parameters, test for fusing current capability, and unclamped inductive load (UIL) or unclamped inductive switching (UIS) test, are important and critical for assurance of the robust product performance, quality and reliability. The fusing current capability test tries to simulate which case has the highest fusing current capability. The fusing current is generally used to determine the maximum current capability of a certain package. An unclamped inductive load represents an extreme electrical stress condition since the energy stored in the inductor during the on-state is dumped directly into the device when it is turned off. The device UIL capability rating is also termed as ldquoruggednessrdquo, which is a scale of how much power the body diode can handle before it is destroyed. During the assembly process, some modifications might be made to achieve high machine throughput without affecting much electrical performance. However, this must be carefully investigated. In this paper the layout of wire bond is thoroughly investigated by experimental work and FEA modeling. The initial design has three 8 mil source wires (3-8) bonded on 3 pads of the die. Two evaluation cases using two 12 mil source wires (2-12) bonded on 2 different pads are studied and compared with the control case. Both current fusing test and UIL test are simulated by FEA. It is indicated that the FEA simulation results have good correlation with the experimental results.
  • Keywords
    electronics packaging; finite element analysis; lead bonding; microassembling; reliability; semiconductor device testing; DC test; FEA modeling; die layout; electrical stress; fusing current capability test; power packages; unclamped inductive load test; unclamped inductive switching test; wire bond; Assembly; Bonding; Diodes; Inductors; Packaging; Robustness; Stress; Testing; Throughput; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems, 2009. EuroSimE 2009. 10th International Conference on
  • Conference_Location
    Delft
  • Print_ISBN
    978-1-4244-4160-0
  • Electronic_ISBN
    978-1-4244-4161-7
  • Type

    conf

  • DOI
    10.1109/ESIME.2009.4938434
  • Filename
    4938434