DocumentCode
3423468
Title
Methodologies for efficient asynchronous circuits design
Author
Li, S. Henry
Author_Institution
Bell Labs., Lucent Technol., Murray Hill, NJ, USA
fYear
1997
fDate
9-11 Mar 1997
Firstpage
154
Lastpage
158
Abstract
This paper describes the approaches for transistor count minimization for asynchronous control modules. In this design, pull-up/pull-down CMOS is used to implement asynchronous (or self-timed) circuits, which are 4-phase handshake rind dual-rail data format. One of the control blocks, IF module, is discussed as an application example. Moreover, the comparison of transistor count between new implementation and conventional design is included. The functional verification is done by SPICE simulation
Keywords
CMOS logic circuits; SPICE; asynchronous circuits; integrated circuit design; logic design; IF module; SPICE simulation; asynchronous circuit design; control module; four-phase handshake rind dual-rail data format; pull-up/pull-down CMOS IC; self-timed circuit; transistor count minimization; Asynchronous circuits; CMOS logic circuits; CMOS technology; Circuit synthesis; Delay; Minimization; Rails; SPICE; Switches; Telecommunication switching;
fLanguage
English
Publisher
ieee
Conference_Titel
System Theory, 1997., Proceedings of the Twenty-Ninth Southeastern Symposium on
Conference_Location
Cookeville, TN
ISSN
0094-2898
Print_ISBN
0-8186-7873-9
Type
conf
DOI
10.1109/SSST.1997.581597
Filename
581597
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