Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity

Novel switched-capacitor (SC) delay circuit architectures, all insensitive to capacitance ratio mismatch, nonideal amplifier´s DC offset and 1/f noise with also either narrow or wideband compensation of finite gain error, will be proposed in this paper. A rigorous comparison of the different structures with respect to magnitude, phase and offset errors will be presented for illustrating their effectiveness. Finally, a flexible implementation of arbitrarily longer delay by the proposed circuits will be further developed in some design examples of unit and double unit delay circuits with only one amplifier and unchanged accuracy performance