DocumentCode
3423665
Title
A high-throughput pipelined architecture for blind adaptive equalization with minimum latency
Author
Mizuno, M. ; Ueda, Kenji ; Okello, James ; Ochi, Hiroshi
Author_Institution
Dept. of Commun. Electr. Eng., Nagano Japan Radio Co., Ltd., Japan
Volume
2
fYear
2002
fDate
3-6 Nov. 2002
Firstpage
980
Abstract
We propose a pipelined architecture for an equalizer based on the multilevel modified constant modulus algorithm (MMCMA). We also provide the correction factor that mathematically converts the adaptive equalizer having the proposed architecture into an equivalent non-pipelined conventional MMCMA based equalizer. The proposed architecture uses modules with 6 filter coefficients, resulting in an overall latency of a single sampling period, along the main transmission line. The basic concepts of the proposed architecture is to implement the finite impulse response (FIR) filter and the algorithm portion of the equalizer, such that the critical path of all circuits has three complex multipliers and three adders.
Keywords
FIR filters; adaptive equalisers; adaptive filters; blind equalisers; digital filters; pipeline processing; FIR adaptive digital filter; FIR filter; adders; blind adaptive equalization; blind equalization; complex multipliers; critical path; filter coefficients; finite impulse response filter; multilevel modified constant modulus algorithm; pipelined architecture; transmission line; Adaptive equalizers; Blind equalizers; Computer architecture; Computer science; Delay; Finite impulse response filter; Pipeline processing; Sampling methods; Systems engineering and theory; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-7803-7576-9
Type
conf
DOI
10.1109/ACSSC.2002.1196930
Filename
1196930
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