DocumentCode
3423678
Title
Reduced complexity LC-LMS joint MMSE equalization and square root raised-cosine matched filter processing via constraint windowing
Author
Bologna, Frank ; Harris, Fred
Author_Institution
SPAWAR Syst. Center, San Diego, CA, USA
Volume
2
fYear
2002
fDate
3-6 Nov. 2002
Firstpage
985
Abstract
Recently, a new class of fractional-spaced equalizers has been developed that perform joint MMSE channel equalization and square-root raised-cosine (RRC) matched filter (MF) processing via the linearly constrained least-mean-square (LC-LMS) algorithm. While the time-multiplexing scheme employed by this joint process equalizer permits a single bank of multipliers to service the demands of both the channel inversion and MF processing so as to conserve the RRC MF FPGA real estate, the demands of an additional responsibility imposed upon the equalizer´s update effectively doubles its computational workload. We present a novel modification to the LC-LMS equalizer that drastically reduces the workload required to develop the RRC MF within the digital equalizer.
Keywords
equalisers; field programmable gate arrays; least mean squares methods; matched filters; multiplying circuits; signal processing; FPGA real estate; LMS algorithm; MMSE equalization; channel equalization; channel inversion; constraint windowing; least-mean-square algorithm; matched filter processing; square root raised-cosine; time-multiplexing; AWGN; Constraint optimization; Equalizers; Equations; Field programmable gate arrays; Matched filters; Pulse amplifiers; Pulse modulation; Redundancy; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-7803-7576-9
Type
conf
DOI
10.1109/ACSSC.2002.1196931
Filename
1196931
Link To Document