FPGA digital down converter IP for SDR terminals

Author

Girau, G. ; Martina, M. ; Molino, A. ; Terreno, A. ; Vacca, F.

Author_Institution

CERCOM (Center for Multimedia Radio Commun.), Politecnico di Torino, Italy

Volume

2

fYear

2002

fDate

3-6 Nov. 2002

Firstpage

1010

Abstract

During the past years, software platforms have proved a superior scalability with respect to hardware solutions. However, wireless communication rates can not be faced resorting only to software. Software defined radio paradigm will try to push reconfigurable blocks as near as possible to the antenna. The first block suitable in this implementation is the digital down converter, needed to adapt higher antenna´s data rate to intermediate frequency ones. In this paper a fully reconfigurable IP of a cascaded integrator comb (CIC) filter, an economical class of multiplier-less filters, is proposed. FPGA implementation has lead to very satisfactory results: 135 MHz on a XCV100E.

Keywords

cascade networks; cellular radio; comb filters; digital filters; field programmable gate arrays; frequency convertors; integrating circuits; software radio; transport protocols; 135 MHz; CIC filter; FPGA digital down converter IP; FPGA implementation; GSM; SDR terminals; XCV100E; antenna data rate; cascaded integrator comb; hardware solutions; intermediate frequency; multiplierless filters; reconfigurable IP; reconfigurable blocks; software defined radio paradigm; software platforms; wireless communication rates; Computer architecture; Field programmable gate arrays; Filters; GSM; Multimedia communication; Radio communication; Receivers; Scalability; Software radio; Streaming media;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-7576-9

Type

conf

DOI

10.1109/ACSSC.2002.1196936

Filename

1196936