High-performance BiCMOS output buffer design strategies

Author

Costa, Pierangelo ; Fiocchi, Carlo ; Gatti, Umberto ; Maloberti, Franco

Author_Institution

Dipt. di Elettronica, Pavia Univ., Italy

Volume

2

fYear

1999

fDate

36342

Firstpage

168

Abstract

This paper discusses design issues for high-performance BiCMOS output buffers, as required in T&Hs and data converters for advanced applications. We compare different topologies and analyze the main limitations. The best solution features a linearity better than -105 dB (HD₃) at an input frequency of 100 MHz. The simulation results referred to a conventional 0.8 μm BiCMOS process cover a huge range of performance parameters in terms of linearity, bandwidth and dynamic range. More in general, this paper helps the designer to identify the best strategy for given high speed and high resolution specifications

Keywords

BiCMOS analogue integrated circuits; buffer circuits; data conversion; sample and hold circuits; 0.8 micron; 100 MHz; BiCMOS; bandwidth; data converters; design strategies; dynamic range; input frequency; linearity; output buffer; performance parameters; track and hold circuits; Bandwidth; BiCMOS integrated circuits; CMOS technology; Degradation; Dynamic range; Frequency; Harmonic distortion; Linearity; MOS devices; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780645

Filename

780645