Title :
A novel analog-digital flash converter architecture based on capacitive threshold gates
Author :
Schmid, A. ; Bowler, D. ; Baumgartner, R. ; Leblebici, Y.
Author_Institution :
Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., MA, USA
Abstract :
In this paper, the circuit architecture and operation of a novel analog-digital flash converter is presented, which is based on cascade-connected capacitive threshold gates. The circuit structure, which is realized using conventional CMOS technology, offers a very small overall layout area, simple operational requirements, and very high input-to-output response speed. Fabricated four-bit flash ADC circuits have been tested to exhibit highly accurate DC transfer characteristics, and typical transient response times in the order of 40 ns. Four-bit and five-bit flash ADC variants can be used as building blocks in high-speed pipelined ADC architectures with higher accuracy
Keywords :
CMOS integrated circuits; analogue-digital conversion; cascade networks; high-speed integrated circuits; pipeline processing; transient response; 40 ns; CMOS technology; DC transfer characteristics; analog-digital flash converter architecture; cascade-connected capacitive threshold gates; high-speed pipelined ADC architectures; input-to-output response speed; operational requirements; overall layout area; transient response times; Analog-digital conversion; Artificial neural networks; CMOS technology; Circuit testing; Computer architecture; Integrated circuit technology; Logic gates; Signal processing; Signal resolution; Silicon;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780646
