Parametric FPGA early-late DLL implementation for a UMTS receiver

Third generation communication schemes, mainly based on the W-CDMA access technique, are replacing second generation ones both in the US and in EU countries. CDMA makes possible simultaneous communications, spreading the user´s information over a large frequency range by means of orthogonal codes. One of the main problems of this type of communication is the need for exact alignment between the received sequence and the locally despreading code. The early-late block is devoted to maintaining this alignment using a delay locked loop, provided that the first alignment is performed by the synchronizer block. A reconfigurable early-late tracking loop architecture, for SDR (software defined radio) implementation, is proposed. Very promising results have been obtained from logical synthesis and from physical implementation on a Xilinx XCV100E (48.7 Mhz, 616 FFs, 719 LUTs).