Title :
An ASIC implementation of adaptive arithmetic coding
Author :
Acunto, Giuseppe ; Sans, Miquel ; Burg, Andreas ; Fichtner, Wolfgang
Author_Institution :
Integrated Syst. Lab., Eidgenossische Tech. Hochschule, Zurich, Switzerland
Abstract :
We present an improved version of an ASIC implementation of the adaptive arithmetic coding algorithm which uses a two-level memory hierarchy. We propose algorithmic modifications and a special hardware structure to speed-up the design without degrading the compression ratio obtained using this memory hierarchy. Moreover, several new features which increase the compression efficiency are introduced. Finally, a VLSI implementation based on the results of our work is presented.
Keywords :
VLSI; adaptive codes; application specific integrated circuits; arithmetic codes; data compression; ASIC implementation; VLSI implementation; adaptive arithmetic coding algorithm; algorithmic modifications; compression efficiency; compression ratio; hardware structure; memory hierarchy; two-level memory hierarchy; Algorithm design and analysis; Application specific integrated circuits; Arithmetic; Decoding; Degradation; Encoding; Equations; Hardware; Laboratories; Very large scale integration;
Conference_Titel :
Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-7576-9
DOI :
10.1109/ACSSC.2002.1196950
