0.18 um dual Vt MOSFET process and energy-delay measurement

A 0.18 um dual Vt MOSFET process has been developed. The low Vt devices are used for logic and the high Vt device for power control. The low Vt NMOS and PMOS have threshold voltages of 80 mV and 100 mV at nominal channel length, and Ion/Ioff of 340/0.05 uA/um and 123/0.03 uA/um respectively under 1V Vdd. The NMOS current drive at 0.6V Vdd has a 40% improvement over the best reported to date. Energy-delay (ED) extracted from measured device data was investigated over Vdd and Vt parameter space for the first time. The results show that: (1) Optimum Vt/Vdd corresponding to minimum energy-delay product for a typical application is around 120/300 mV and leads to modest performance. (2) The optimum Vt is a logarithmic function of the typical activity factor of the application. (3) The dual Vt process is important for applications with high idling factor and brings about a 2.5X improvement in energy-delay product or 50% improvement in speed with the same energy over a single standard Vt process for an application with a 98% idling factor.