Title :
Optimal transistor sizing for CMOS VLSI circuits using modular artificial neural networks
Author_Institution :
Dept. of Electr. Eng., Hartford Univ., West Hartford, CT, USA
Abstract :
The unpredictable variation in microelectronic circuits due to process tolerances increases significantly with increased levels of miniaturization. If ignored, the variation will result in poor manufacturing yield. If a worst-case approach is adopted, a loss of competitive edge results. This situation provides the motivation for efficient robust design of VLSI circuits. A method is proposed which generates a modular neural network MANN for mapping process level parameters to circuit performance. The MANN-an adaptive mixture of local experts competing to learn different aspects of a problem-is employed in performing extremely efficient optimization of the circuit yield at minimal cost. The MANN calculates circuit performance and optimizes yield with 97% accuracy at 20% of the cost of a full SPICE simulation
Keywords :
CMOS integrated circuits; VLSI; circuit CAD; integrated circuit design; integrated circuit yield; neural nets; CMOS VLSI circuits; MANN; circuit yield; local experts; manufacturing yield; modular artificial neural networks; process level parameters; process tolerances; robust design; transistor sizing; worst-case approach; Artificial neural networks; Circuit optimization; Cost function; Fabrication; Manufacturing; Microelectronics; Neural networks; Probability; Robustness; Very large scale integration;
Conference_Titel :
System Theory, 1997., Proceedings of the Twenty-Ninth Southeastern Symposium on
Conference_Location :
Cookeville, TN
Print_ISBN :
0-8186-7873-9
DOI :
10.1109/SSST.1997.581646
