Title :
A digital technique for reducing clock jitter effects in time-interleaved A/D converter
Author :
Jin, Huawen ; Lee, Edward K F
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Abstract :
Time-interleaved A/D converter is an effective approach to increase the data throughput. However, it suffers from clock jitter existing in the multi-phase clocks, which degrade the converter´s Spurious-Free-Dynamic-Range (SFDR) as well as the Signal-to-Noise Ratio (SNR). In this paper, a digital technique is proposed to reduce these non-ideal effects by obtaining a better estimation on the output data through the use of interpolation. Simulation results show that the proposed technique significantly improves the SFDR by 20~50 dB
Keywords :
analogue-digital conversion; interpolation; timing jitter; A/D converter; SNR degradation; clock jitter effects reduction; digital technique; interpolation; multi-phase clocks; nonideal effects; spurious-free-dynamic-range degradation; time-interleaved ADC; Clocks; Degradation; Error correction; Interpolation; Jitter; Linearity; Sampling methods; Signal generators; Signal to noise ratio; Throughput;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780726
