DocumentCode
342441
Title
High resolution rail-to-rail ADC in CMOS digital technology
Author
Gardino, Daniele ; Maloberti, Franco
Author_Institution
Dipt. di Elettronica, Pavia Univ., Italy
Volume
2
fYear
1999
fDate
36342
Firstpage
339
Abstract
This paper discusses the design issues for an high resolution rail-to-rail analog-to-digital converter. The circuit proposed uses conventional digital technology (without precise capacitors) and allows 12 bits of resolution to be achieved using 2.4 V bias and 2.4 V input dynamic range. The proposed architecture is based on the successive algorithm technique and uses a rail-to-rail autozeroed comparator. A method to digitally correct errors from the first part of the conversion cycle is also discussed
Keywords
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); error correction; 12 bit; 2.4 V; CMOS digital technology; analog-to-digital converter; design issues; digital error correction; high resolution ADC; rail-to-rail ADC; rail-to-rail autozeroed comparator; successive algorithm technique; CMOS technology; Capacitors; Circuits; Clocks; Dynamic range; Error correction; Linearity; Resistors; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.780728
Filename
780728
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