A neuron-MOS parallel associator for high-speed CDMA matched filter

Neuron MOS (νMOS) technology has been applied to build a matched filter for CDMA. Based on the parallel search architecture of νMOS associator, an input signal train captured by sample and hold circuits is simultaneously matched with a group of templates having all possible shifts in phase of an identical PN (pseudorandom noise) code. The maximum correlation is detected by fully parallel comparison using the binary-search νMOS winner-take-all circuit. Such a parallel architecture enables us to perform very fast peak detection as well as the detection of second and third correlation peaks arising from multipath delays. Moreover, the binary-search WTA provides the degree of matching in a binary code, thus enabling more advanced applications. For instance, it is possible to cascade the system in multiple stages and apply it to much longer-chip-length PN codes. Test chips were fabricated in a 0.6-μm double-poly triple-metal CMOS technology and the fundamental operation of the system has been experimentally demonstrated