An area-efficient analog VLSI architecture for state-parallel Viterbi decoding

Author

He, Kai ; Cauwenberghs, Gert

Author_Institution

Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

Volume

2

fYear

1999

fDate

36342

Firstpage

432

Abstract

An area-efficient analog VLSI architecture is presented to implement a low-power, state-parallel, rate R=1/2, constraint length K=7 Viterbi decoder. A combination of current-mode and switched-capacitor techniques are used in designing the add-compare-select (ACS) module, resulting into a very compact VLSI architecture, implemented in a 64-state hard-decision Viterbi ACS VLSI chip fabricated in a 2 μm CMOS process through MOSIS. The chip has been tested to operate at 500 kbps data rate and 7.65 mW power dissipation

Keywords

CMOS analogue integrated circuits; VLSI; Viterbi decoding; analogue processing circuits; current-mode circuits; low-power electronics; 2 micron; 500 kbit/s; 7.65 mW; CMOS process; Viterbi decoder; add-compare-select module; area-efficient analog VLSI architecture; constraint length; current-mode techniques; hard-decision Viterbi ACS VLSI chip; low-power electronics; power dissipation; state-parallel Viterbi decoding; switched-capacitor techniques; CMOS technology; Computer architecture; Convolutional codes; Digital communication; Energy consumption; Maximum likelihood decoding; Memory management; Mobile communication; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780756

Filename

780756