Title :
High speed interface for system-on-chip design by self-tested self-synchronization
Author :
Mu, Fenghao ; Svensson, Christer
Author_Institution :
SwitchCore, Lund, Sweden
Abstract :
Global synchronization has been commonly used to protect clocked I/O from data read failure due to metastability. For future high performance system-on-chip design, global synchronization is more difficult as both frequency and chip size increase quickly. This paper addresses a mesochronous clocking (MC) strategy which can be implemented with three self-tested self-synchronization (STSS) methods for parallel data transfer between processing elements (PEs). Compared with global synchronization, MC has many advantages: lower process cost; less power dissipation in clock distribution; no limit in system scale; less delay in long distance data transfer; more simplicity and flexibility in design. The STSS implementations are also very simple and robust, and the metastability in data read is avoided because STSS is completely insensitive to both clock skew and data delay
Keywords :
VLSI; application specific integrated circuits; circuit CAD; circuit stability; clocks; delays; integrated circuit design; integrated circuit interconnections; logic CAD; synchronisation; chip size; clock distribution; clock skew; clocked I/O; data delay; data read failure; data transfer; global synchronization; high speed interface; mesochronous clocking; metastability; parallel data transfer; power dissipation; process cost; self-tested self-synchronizatlon; system-on-chip design; Built-in self-test; Clocks; Costs; Delay systems; Frequency synchronization; Metastasis; Power dissipation; Protection; Robustness; System-on-a-chip;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780795
