DocumentCode
342485
Title
A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range
Author
Sung, Hyuk-Jun ; Yoon, Kwang Sub
Author_Institution
Dept. of Electron. Eng., Inha Univ., Inchon, South Korea
Volume
2
fYear
1999
fDate
36342
Firstpage
553
Abstract
This paper describes a dual-looped PLL architecture to improve voltage-to-frequency linearity of the VCO. The designed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good linearity. A PFD circuit preventing fluctuation of the charge pump circuit under the locked condition is designed. Experimental results show that the phase noise of the VCO with a V-I converter is -100.3 dBc/Hz at a 100 kHz offset frequency and the power dissipation is 92 mW
Keywords
CMOS integrated circuits; high-speed integrated circuits; phase locked loops; voltage-controlled oscillators; 3 to 250 MHz; 3.3 V; 74.8 MHz to 1 GHz; 92 mW; PFD circuit; V/I converter; charge pump circuit; dual-looped PLL architecture; high speed CMOS PLL; locking range; phase noise; voltage-to-frequency linearity; Charge pumps; Circuits; Fluctuations; Frequency conversion; Linearity; Phase frequency detector; Phase locked loops; Phase noise; Voltage; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.780811
Filename
780811
Link To Document