Title :
VLSI design of a modulo-extractor
Author :
Sivakumar, R. ; Dimopulos, N.J. ; Li, K.F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
Abstract :
A VLSI design of a modulo-extractor based on the principles of residue arithmetic is discussed. A method for computing (X)m for specific values of m is analyzed, and the area-time complexity has been implemented in 3 μm CMOS3DLM technology. Simulation results have yielded a propagation delay of less than 100 ns
Keywords :
CMOS integrated circuits; VLSI; digital arithmetic; logic design; 100 ns; 3 micron; CMOS IC; CMOS3DLM technology; VLSI design; digital arithmetic; modulo-extractor; propagation delay; residue arithmetic; Application software; CMOS technology; Circuit simulation; Computational modeling; Design engineering; Digital arithmetic; Digital circuits; Hardware; Propagation delay; Very large scale integration;
Conference_Titel :
Communications, Computers and Signal Processing, 1991., IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
0-87942-638-1
DOI :
10.1109/PACRIM.1991.160745
