A monolithic 1.25 Gbits/sec CMOS clock/data recovery circuit for fibre channel transceiver

Author

Wu, L. ; Chen, H. ; Nagavarapu, S. ; Geiger, R. ; Lee, E. ; Black, W.

Author_Institution

Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA

Volume

2

fYear

1999

fDate

36342

Firstpage

565

Abstract

This paper describes a monolithic CMOS clock/data recovery PLL circuit for 1.25 Gbits/sec fibre channel transceiver. Features include a fully differential high speed phase detector, high speed charge pump, and a 4-stage ring oscillator which is optimized to have enough tuning range to cover all process corners as well as temperature variation from 0°C~100°C. The circuit was designed in 0.35 μm single-poly, triple metal CMOS process. Simulations indicate that the core circuit along with the output buffer consumes 220 mW from a single 3.3 V supply in which 60 mW is dissipated by the core circuit itself

Keywords

CMOS digital integrated circuits; circuit tuning; digital phase locked loops; optical communication equipment; optical fibre communication; phase detectors; synchronisation; transceivers; 0 to 100 degC; 0.35 micron; 1.25 Gbit/s; 220 mW; 3.3 V; 60 mW; PLL circuit; clock/data recovery circuit; fibre channel transceiver; four-stage ring oscillator; fully differential high speed phase detector; high speed charge pump; output buffer; temperature variation; triple metal CMOS process; tuning range; Charge pumps; Circuit optimization; Clocks; Detectors; Phase detection; Phase locked loops; Ring oscillators; Temperature distribution; Transceivers; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780816

Filename

780816