Customized instruction-sets for embedded processors

Author

Fisher, Joseph A.

Author_Institution

Hewlett-Packard Labs. Cambridge, MA, USA

fYear

1999

fDate

1999

Firstpage

253

Lastpage

257

Abstract

It is generally believed that there will be little more variety in CPU architectures, and thus the design of Instruction-Set Architectures (ISAs) will have no role in the future of embedded CPU design. Nonetheless, it is argued in this paper that architectural variety will soon again become an important topic, with the major motivation being increased performance due to the customization of CPUs to their intended use. Five major barriers that could hinder customization are described, including the problems of existing binaries, toolchain development and maintenance costs, lost savings/higher chip cost due to the lower volumes of customized processors, added hardware development costs, and some factors related to the product development cycle for embedded products. Each is discussed, along with potential, sometimes surprising, solutions

Keywords

instruction sets; logic CAD; microprocessor chips; parallel architectures; VLIW; chip cost; customized instruction-sets; customized processors; embedded CPU design; embedded processors; hardware development costs; instruction-set architectures; maintenance costs; product development cycle; toolchain developmen; Application software; Computer architecture; Costs; Hardware; Instruction sets; Laboratories; Lead compounds; Microprocessors; Permission; Personal digital assistants;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings. 36th

Conference_Location

New Orleans, LA

Print_ISBN

1-58113-092-9

Type

conf

DOI

10.1109/DAC.1999.781321

Filename

781321