Title :
Performance study of virtual-channel router for Network-on-Chip
Author :
Liu, Feiyang ; Gu, Huaxi ; Yang, Yintang
Author_Institution :
State Key Lab. of Integrated Service Networks, Xidian Univ., Xi´´an, China
Abstract :
Network-on-Chip (NoC) overcomes the main constraints of traditional bus-based System-on-Chip (SoC). It introduces the principle of interconnection network into SoC design. Router is the main component of NoC and determines performance to a large extend. Virtual-channel router is one of the promising router architectures for Network-on-Chip, for its low delay and high network throughput. In this paper, we evaluate the performance of virtual-channel router with different buffer schemes. Various simulations are carried out and the analysis of the simulation results help to achieve a better configuration for virtual-channel router, considering network performance and buffer requirement.
Keywords :
buffer circuits; delays; integrated circuit design; integrated circuit interconnections; network routing; network-on-chip; SoC design; buffer requirement; delay; interconnection network; network throughput; network-on-chip; router architectures; virtual-channel router; Analytical models; Bandwidth; Communication networks; Computer architecture; Costs; Design methodology; Multiprocessor interconnection networks; Network interfaces; Network-on-a-chip; System-on-a-chip; Network-on-Chip; performance evaluation; router architecture; virtual-channel router;
Conference_Titel :
Computer Design and Applications (ICCDA), 2010 International Conference on
Conference_Location :
Qinhuangdao
Print_ISBN :
978-1-4244-7164-5
Electronic_ISBN :
978-1-4244-7164-5
DOI :
10.1109/ICCDA.2010.5541185
