A high performance 0.35 μm 3.3 V BiCMOS technology optimized for product porting from a 0.6 μm 3.3 V BiCMOS technology

Author

Schütz, Joseph ; Bohr, Mark

Author_Institution

Portland Technol. Dev., Intel Corp., Aloha, OR, USA

fYear

1995

fDate

2-3 Oct 1995

Firstpage

43

Lastpage

46

Abstract

A 0.35 μm logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5 V version offers lower power and higher performance. A 3.3 V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6 μm 3.3 V BiCMOS process. The design process for converting an existing production worthy 0.6 μm 3.3 V BiCMOS design is described. The silicon results are described

Keywords

BiCMOS digital integrated circuits; BiCMOS logic circuits; elemental semiconductors; integrated circuit design; integrated circuit technology; logic design; silicon; 0.35 micron; 2.5 V; 3.3 V; Si; design process; high performance BiCMOS technology; logic technology; planarized metal interconnect; product porting; BiCMOS integrated circuits; Capacitance measurement; Capacitance-voltage characteristics; Computational Intelligence Society; Dielectrics; Size measurement; Thickness measurement; Tin; Tungsten; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 1995., Proceedings of the 1995

Conference_Location

Minneapolis, MN

Print_ISBN

0-7803-2778-0

Type

conf

DOI

10.1109/BIPOL.1995.493862

Filename

493862