DocumentCode
3425638
Title
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry
Author
Higeta, Keiichi ; Usami, Masami ; Ohayashi, Masayuki ; Fujimura, Yasuhiro ; Nishiyama, Masahiko ; Isomura, Satoru ; Yamaguchi, Kunihiko ; Idei, Youji ; Nambu, Hiroaki ; Ohhata, Kenichi ; Hanta, Nadateru
Author_Institution
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
fYear
1995
fDate
2-3 Oct 1995
Firstpage
47
Lastpage
50
Abstract
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed
Keywords
CMOS memory circuits; SRAM chips; emitter-coupled logic; integrated circuit testing; logic gates; 0.9 ns; 1.15 Mbit; 30 ps; ECL-CMOS SRAM; current source; logic gates; memory-cell test; on-chip test circuitry; reliability; soft-error-immune memory cell; stability; CMOS logic circuits; Circuit stability; Circuit testing; Logic circuits; Logic devices; Logic gates; Logic testing; Random access memory; Read-write memory; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar/BiCMOS Circuits and Technology Meeting, 1995., Proceedings of the 1995
Conference_Location
Minneapolis, MN
Print_ISBN
0-7803-2778-0
Type
conf
DOI
10.1109/BIPOL.1995.493863
Filename
493863
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