Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD/EOS performance of a 0.25 /spl mu/m CMOS process

In this paper we show for the first time, how junction depths and salicide thicknesses in a 0.25 /spl mu/m CMOS process affect the current gain /spl beta/ of a self-biased lateral NPN transistor, and examine the relationship between /spl beta/ and the ESD performance. Furthermore, we present a direct method for extracting the self-biased LNPN /spl beta/ and hence characterize the transistor behavior. Devices with lower /spl beta/ are found to have lower ESD performance. /spl beta/ is observed to be strongly influenced by the effective drain/source diffusion depth below the salicide which is determined by the implant energy as well as the amount of active diffusion consumed in silicidation. Substrate resistance as determined by the epitaxial thickness is also shown to be an important parameter defining ESD performance. Possible design trade-offs are discussed.