Title :
Low-power design methodology for Gbit/s bipolar LSIs
Author :
Koike, Keiichi ; Kawai, Kenji ; Onozawa, Akira ; Kobayashi, Yoshiji ; Ichino, Harubiko
Author_Institution :
NTT LSI Labs., Kanagawa, Japan
Abstract :
A low-power Gbit/s operating bipolar standard cell LSI design methodology is described. It features a performance-driven layout, highly accurate static timing analysis, and CAD-based optimization for power dissipation. A 5.6-k-gate SDH signal-processing LSI operates at 1.6 Gbit/s with only 3.9 W power consumption
Keywords :
bipolar digital integrated circuits; cellular arrays; integrated circuit design; large scale integration; 1.6 Gbit/s; 3.9 W; CAD-based optimization; SDH signal-processing; bipolar LSIs; low-power design methodology; performance-driven layout; power dissipation; standard cell; static timing analysis; Circuits; Clocks; Delay; Design automation; Design methodology; Large scale integration; Performance analysis; Power dissipation; Timing; Wire;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 1995., Proceedings of the 1995
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-2778-0
DOI :
10.1109/BIPOL.1995.493876
