Title :
PLAGA: a highly parallelizable genetic algorithm for programmable logic arrays test pattern generation
Author :
Cruz, Alfredo ; Mukherjee, Sumitra
Author_Institution :
Dept. of Comput. Inf. Syst., EDP Coll. of Puerto Rico, Hato Rey, Puerto Rico
Abstract :
An evolutionary algorithm (EA) approach is used to generate test vectors for the detection of shrinkage faults in programmable logic arrays (PLA). Three basic steps are performed during the generation of the test vectors: crossover, mutation and selection. A new mutation operator is introduced that helps increase the Hamming distance among the candidate solutions. Once crossover and mutation have occurred, the new candidate test vectors with higher fitness function scores replace the old ones. With this scheme, population members steadily improve their fitness level with each new generation. The resulting process yields improved solutions to the problem of the PLA test vector generation for shrinkage faults. PLA testing and fault simulation is computationally prohibitive in uniprocessor machines. However, PLAGA is well suited for powerful parallel processing machines with vectorization capability,
Keywords :
fault simulation; genetic algorithms; logic testing; parallel processing; programmable logic arrays; Hamming distance; PLA test vector generation; PLAGA; candidate solutions; crossover; evolutionary algorithm; fault simulation; fitness function; highly parallelizable genetic algorithm; mutation; parallel processing machines; programmable logic arrays test pattern generation; selection; shrinkage faults; vectorization; Computational modeling; Evolutionary computation; Fault detection; Genetic algorithms; Genetic mutations; Hamming distance; Logic testing; Parallel processing; Performance evaluation; Programmable logic arrays;
Conference_Titel :
Evolutionary Computation, 1999. CEC 99. Proceedings of the 1999 Congress on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5536-9
DOI :
10.1109/CEC.1999.782524