VLSI Implementation of fully pipelined multiplierless 2D DCT/IDCT architecture for JPEG

The Discrete Cosine transform is widely used as the core of digital image compression. Discrete cosine transforms attempts to de-correlate the image data. After decor relation, each transform coefficient can be encoded independently without losing compression efficiency. In this paper we present VLSI Implementation of fully pipelined multiplierless architecture of 8 × 8 2D DCT/IDCT. This architecture is used as the core of JPEG compression hardware. The 2-D DCT calculation is made using the 2-D DCT separability property, such that the whole architecture is divided into two 1-D DCT calculations by using a transpose buffer. The architecture described to implement 1-D DCT is based on Binary-Lifted DCT. The 2-D DCT architecture achieves an operating frequency of 166 MHz. One input block of 8 × 8 samples each of 8 bits each is processed in 0.198μs. The pipeline latency of proposed architecture is 45 Clock cycles.