A new adiabatic technique for designing low power array architectures

A new approach for implementing low power array architectures based on energy recovery techniques (i.e. adiabatic switching) is introduced. The main principles of the reversible pipeline are adopted. However, its large hardware complexity does not allow efficient implementations. Exploiting the inherent property of a reversible pipeline system that the “reverse” logic blocks are used in different time instances and the characteristic that several applications have identical logic blocks, we can reduce the hardware complexity significantly. Here, emphasis is given to the hardware reduction and function of the proposed reversible pipeline architectures. Using an appropriate multiplexer and clocking strategy, we can achieve the reversible operation with small hardware cost. The proposed approach is suitable for implementing array processor architectures, which realize a certain class of Digital Signal Processing (DSP) applications