Two on-chip bandwidth calibration methods for phase-locked loops used in wireless transceiver applications

Phase-locked loops (PLL) are essential building blocks in wireless transceivers. Concerning data transmission and reception the performance of the PLL is crucial for the overall performance of the whole system. The transmitter architecture of the presented system does not use mixers but the PLL itself for FSK modulation. Therefore especially the bandwidth of the PLL influences performance parameters. As the PLL bandwidth is subject to significant variations due to process, temperature and supply voltage, bandwidth calibration is an important measure to ensure the PLL performance specifications. This paper presents two methods which use building blocks of an existing transceiver to calibrate the PLL bandwidth. Both methods use existing features of the transceiver architecture and therefore require only minimal adjustments and in principal no additional building blocks in order to accomplish bandwidth calibration. The first method uses an ADC to measure the PLL Loop Filter Voltage and the second employs the receiver to observe the frequency and phase of the PLL output signal. The proposed methods have been verified by measurements using a test chip implemented in a low-cost Infineon 130 nm CMOS process and an FPGA board. The variation of the PLL bandwidth after calibration is lower than ±10% compared to more than ±60% for an uncalibrated PLL. The time needed for calibration lies between 32 μs and 200 μs.