• DocumentCode
    3428775
  • Title

    A sixteen level scheme enabling 64 Mbit flash memory using 16 Mbit technology

  • Author

    Kencke, D.L. ; Richart, R. ; Garg, S. ; Banerjee, S.K.

  • Author_Institution
    Microelectron. Res. Center, Texas Univ., Austin, TX, USA
  • fYear
    1996
  • fDate
    8-11 Dec. 1996
  • Firstpage
    937
  • Lastpage
    939
  • Abstract
    Multilevel flash memories have been shown to double storage capacity without changing device dimensions. In this work, it is demonstrated for the first time that sixteen levels can be stored within a small 2.5 V spread, quadrupling memory size with four bits/cell. A new method is used to calculate programmed threshold voltages, V/sub t/´s, showing that transistor V/sub t/´s may overlap while logical V/sub t/´s remain distinct. A ten-year equivalent data retention bake demonstrates the feasibility of this approach for producing 64 Mbit storage capacity using existing 16 Mbit NOR stacked-gate technology.
  • Keywords
    EPROM; integrated memory circuits; 64 Mbit; NOR stacked-gate technology; data retention bake; multilevel flash memory; storage capacity; threshold voltage; Automatic programming; Automatic testing; Charge measurement; Current measurement; EPROM; Flash memory; Microelectronics; Solid state circuits; Threshold voltage; Transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1996. IEDM '96., International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-3393-4
  • Type

    conf

  • DOI
    10.1109/IEDM.1996.554134
  • Filename
    554134