A macro-modeling approach for through silicon via

Modeling parasitic parameters of Through-Silicon Via (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circuits and interconnections in three-dimensional (3D) Integrated Circuits (ICs). This paper presents a complete set of self-consistent equations including self and coupling terms for capacitance of general multi-TSV structures. The error when using the closed form expressions as compared to a field solver is less than 7%. As TSV parasitic capacitance is less than other conventional IO structures´ capacitance, therefore TSV technology results in lower I/O power consumption, which makes it suitable for low power applications.