Title :
Determining redundancy requirements for memory arrays with critical area analysis
Author :
Segal, Julie D. ; Bakarian, Sergei ; Colburn, Jonathon E. ; Kumar, Madan ; Hong, Chang ; Shubat, Alex
Author_Institution :
HPL Inc., San Jose, CA, USA
Abstract :
Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can determine the optimum redundancy configuration for any memory circuit. The technique predicts the yield for a range of redundancy configurations and finds the optimum number of redundant rows and columns for any memory design based on yield and die size considerations
Keywords :
cellular arrays; electrical faults; integrated circuit layout; integrated circuit reliability; integrated circuit yield; integrated memory circuits; probability; redundancy; cell layout; critical area analysis; die size considerations; electrical faults; inline defect data; memory arrays; optimum redundancy configuration; redundancy requirements; redundant columns; redundant rows; rule-based algorithm; yield prediction; Circuit faults; Circuit simulation; Data mining; Electrical capacitance tomography; Lakes; Logic; Predictive models; Probability; Random access memory; Redundancy;
Conference_Titel :
Memory Technology, Design and Testing, 1999. Records of the 1999 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-0259-8
DOI :
10.1109/MTDT.1999.782683
