Asynchronous control of low-power gated-clock finite-state-machines

Author

Oelmann, Bengt ; O´Nils, Mattias

Author_Institution

Dept. of Inf. Technol., Univ. of Mid-Sweden, Sundsvall, Sweden

Volume

2

fYear

1999

fDate

5-8 Sep 1999

Firstpage

915

Abstract

An efficient approach to reduce power consumption in a synchronous Finite-State Machine (FSM) is to de-compose it, according to a partitioning algorithm, to a number of sub-FSMs that interact through some communication signals. Only one sub-FSM is clocked at a time and low power operation is obtained by only clocking the active sub-FSM. In this paper we introduce a new asynchronous communication control for the interacting sub-FSMs, which reduces the total capacitance switched by the system clock. Experimental results show that this leads to significant power savings when the FSM is partitioned into many sub-FSMs

Keywords

CMOS logic circuits; capacitance; finite state machines; logic partitioning; low-power electronics; timing; asynchronous communication control; clocking; finite-state-machines; low-power gated-clock FSM; partitioning algorithm; power consumption reduction; sub-FSMs; synchronous FSM; total capacitance reduction; Asynchronous communication; Automatic control; CMOS integrated circuits; Capacitance; Clocks; Communication system control; Energy consumption; Information technology; Optimization methods; Power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.813263

Filename

813263