Title :
System-Level Modeling of a NoC-Based H.264 Decoder
Author :
Agarwal, Ankur ; Iskander, Cyril-Daniel ; Kalva, Hari ; Shankar, Ravi
Author_Institution :
Dept of Comput. Sci. & Eng., Florida Atlantic Univ., Boca Raton, FL
Abstract :
Networks-on-chip (NoC) are expected to play a key role in future embedded systems. A NoC-based system has the potential to support concurrent processing, in both software and hardware. This can however lead to concurrency issues. We present a multiprocessor system modeling and performance evaluation approach that addresses concurrency. We illustrate our methodology by mapping a H.264 decoder onto a 4 x 3 mesh- based NoC architecture. We show latency, area, and power consumption results for this NoC architecture abstracted from its FPGA implementation.
Keywords :
embedded systems; multiprocessing systems; network-on-chip; performance evaluation; FPGA; H.264 decoder; multiprocessor system modeling; networks-on-chip; performance evaluation; system level modeling; Computer architecture; Concurrent computing; Decoding; Delay; Embedded system; Energy consumption; Hardware; Multiprocessing systems; Network-on-a-chip; Power system modeling; H.264; MLDesigner; NoC; concurrency; network-on-chip;
Conference_Titel :
Systems Conference, 2008 2nd Annual IEEE
Conference_Location :
Montreal, Que.
Print_ISBN :
978-1-4244-2149-7
Electronic_ISBN :
978-1-4244-2150-3
DOI :
10.1109/SYSTEMS.2008.4519008
