Using the EPLL algorithm as a preprocessor for fault analysis

This paper presents a method for fault analysis in power system which uses the concept of enhanced phase-locked loop (EPLL). The proposed method uses an edge detection strategy to properly re-adjust the system state variables in order to achieve fast and smooth behavior during the initial periods after the inception and/or clearance of a fault. Digital implementation of the algorithm is discussed and simulation results obtained by applying the proposed method to experimental data are presented.