DocumentCode
3429691
Title
A Parallel Double-Step CORDIC Algorithm for Digital Down Converter
Author
Wang Han ; Zheng Yousi ; Lin Xiaokang
Author_Institution
Dept. of Electron. Eng., Tsinghua Univ., Beijing
fYear
2009
fDate
11-13 May 2009
Firstpage
257
Lastpage
261
Abstract
The coordinate rotation digital computer (CORDIC) algorithm is a widely studied and hardware-efficient iterative algorithm for evaluating many arithmetic operations. In this paper, we propose a parallel double step CORDIC algorithm. All rotation directions can be predicted in parallel while two rotations are processed in each iteration. The novel hybrid algorithm achieves much less delay and similar throughput compared with parallel CORDIC algorithm. Based on the new algorithm, we also provide a digital down converter architecture using dual CORDIC processor to eliminate both multiplier and CORDIC scale factor.
Keywords
convertors; digital arithmetic; direct digital synthesis; iterative methods; coordinate rotation digital computer algorithm; digital down converter architecture; hardware-efficient iterative algorithm; parallel double-step CORDIC algorithm; Application software; Circuits; Communication networks; Computer networks; Concurrent computing; Delay; Digital arithmetic; Frequency synthesizers; Iterative algorithms; Throughput; CORDIC; digital down converter; double step; parallel CORDIC;
fLanguage
English
Publisher
ieee
Conference_Titel
Communication Networks and Services Research Conference, 2009. CNSR '09. Seventh Annual
Conference_Location
Moncton, NB
Print_ISBN
978-1-4244-4155-6
Electronic_ISBN
978-0-7695-3649-1
Type
conf
DOI
10.1109/CNSR.2009.47
Filename
4939135
Link To Document