The design of high speed UART

This paper focuses on the design of high speed UART. The paper starts by describing the behaviour of UART circuit using VHDL. In the result and simulation part, this paper will focus on the bit errors detection. Besides, in the baud rate generator part, the baud rate generator is incorporated into the UART design before the overall design is synthesized. In the synthesizing part, the VHDL description was translated into a circuit diagram. VHDL synthesis is for high reliability systems. The simulated waveform is completed in 0.395 mus (baud rate of 20.2532 Mbps), 19.2 mus (baud rate of 416.6667 kbps), 211.2 mus (baud rate of 37.8787 kbps) and 1.6448 mus (baud rate of 4.8638 kbps) using 20 MHz clock cycle. The simulated waveforms in this paper have proven the reliability of the VHDL implementation to describe the characteristics and the architecture of the design UART with baud rate generator