Title :
Design of run-time fault-tolerant arrays of self-checking processing elements
Author_Institution :
Inst. fuer Theor. Nachrichtentech. und Informationsverarbeitung, Hannover Univ., Germany
Abstract :
A design method for array architectures from regular dependence graphs (DGs) is extended for the design of reconfigurable arrays. The original design method is combined to a single step mapping of the DG with arbitrary dimension n onto the final signal flow graph (SFG) with dimension k. This eliminates the need for recursive application of a mapping which reduces the dimension of the DG by one, and it is possible to separate the node mapping from the derivation of the time schedule. Sufficient conditions for a valid mapping are given. Then a reconfigurable DG (RecDG) and a reconfiguration control DG (RecCDG) are introduced, which can be mapped onto an SFG using the same procedure as for the nonredundant DG. It is explained how to obtain the RecDG and the RecCDG from the DG. As an example the design procedure is applied to matrix-matrix multiplication
Keywords :
fault tolerant computing; multiprocessing systems; systolic arrays; array architectures; design method; design procedure; fault-tolerant arrays; matrix-matrix multiplication; reconfigurable arrays; regular dependence graphs; self-checking processing elements; signal flow graph; single step mapping; Algorithm design and analysis; Circuit faults; Design methodology; Error correction codes; Fault tolerance; Redundancy; Runtime; Signal mapping; Size control; Very large scale integration;
Conference_Titel :
Application Specific Array Processors, 1990. Proceedings of the International Conference on
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-9089-5
DOI :
10.1109/ASAP.1990.145453
