A real-time software programmable processor for HDTV and stereo scope signals

The architecture is an expanded version of a previously reported video signal processor in which a number of parallel processor clusters can be combined in a tandem connection form or in a parallel connection form. The new video signal processor introduces programmable time-expansion and time-compression circuits to A-to-D and D-to-A converters, respectively, for coping with high speed HDTV signals. It also employs input/output switch units before and after parallel processor clusters. The introduction of input/output switch units to the parallel processor clusters makes it possible to input several video signals simultaneously. By these additional units, a HDTV signal is converted to a set of NTSC level video signals in the time-expansion circuit. Every NTSC level video signal is then delivered to parallel processor clusters through an input switch unit. After processing in clusters, NTSC level signals are converted to a HDTV signal through an output switch unit and time-compression circuits. This architecture can be applied to stereo scope processing