Title :
A 3-D wafer scale architecture for early vision processing
Author :
Toborg, Scott T.
Author_Institution :
Hughes Res. Lab., Malibu, CA, USA
Abstract :
A massively parallel SIMD cellular computer is designed for processing early vision algorithms based on regularization theory and Markov random field (MRF) models. Algorithmic requirements and implementation issues are reviewed in detail for edge detection/surface reconstruction. The development of 3-D wafer scale integration (WSI) technologies that offer an ideal medium for implementing many early vision algorithms is discussed. An edge detection algorithm is mapped to the 3-D WSI computer that consists of a 128×128 array of processors formed by stacking 15 four inch CMOS wafers. This mapping is used as the basis for an enhanced array processor tailored for multiresolution MRF processing. Enhancements are proposed that would boost peak performance to over a trillion operations per second, using a stack of 40 wafers, with a total system volume of 820 cm3 and consuming about 370 W
Keywords :
CMOS integrated circuits; VLSI; computerised picture processing; packaging; parallel architectures; parallel machines; systolic arrays; 3-D WSI computer; 3-D wafer scale architecture; 370 W; 4 in; CMOS; Markov random field models; array of processors; early vision processing; edge detection algorithm; enhanced array processor; four inch wafers; massively parallel SIMD cellular computer; multiresolution MRF processing; regularization theory; surface reconstruction; system volume; wafer stacking; Algorithm design and analysis; Computer architecture; Computer vision; Concurrent computing; Image edge detection; Markov random fields; Process design; Semiconductor device modeling; Surface reconstruction; Wafer scale integration;
Conference_Titel :
Application Specific Array Processors, 1990. Proceedings of the International Conference on
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-9089-5
DOI :
10.1109/ASAP.1990.145462
