Hardware-software co-design of G729 voice encoder using Virtex-II ProTM FPGA

Conjugate-structure algebraic CELP (CS-ACELP) is a type of voice coder algorithm that compresses speech signal based on model parameters of human voice. Fully Software or Hardware implementation of CS-ACELP is not satisfactory in some applications such as multi-channel implementation. So in this paper a hardware-software Co-design implementation of the voice encoder is described. This design is based on idea of parallelism and fast access to data memory using hardware. The proposed system is implemented on Virtex-II Pro^TM FPGA using EDK8.1. The results of experiment show that co-design implantation can reduce the execution time of algorithm and make it possible to multi-channel implementation of it.