Channel complexity analysis for reconfigurable VLSI/WSI processor arrays

Author

Rhee, Phill K. ; Kim, Jung H.

Author_Institution

Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

fYear

1990

fDate

5-7 Sep 1990

Firstpage

329

Lastpage

340

Abstract

The authors propose a general method to analyze channel complexity for a 2D array with a given domain constraint. A domain-based reconfiguration scheme can be divided into two phases: assignment and interconnection. In the assignment phase a logical cell is assigned to a fault-free cell under a domain constraint by assignment rules. In the interconnection phase connections between the assigned logical cells are determined. A domain may be decided considering predetermined maximum distance between two logically adjacent cells. Interconnection redundancy, is represented by channel complexity, where channel complexity is measured by the number of tracks and associated switches. The array is partitioned into as small units, called subranges, as possible while preserving the characteristics of array reconfigurability. Channel complexity is analyzed based on subranges

Keywords

VLSI; fault tolerant computing; microprocessor chips; parallel architectures; redundancy; 2D array; VLSI; WSI; assignment rules; channel complexity; complexity analysis; domain-based reconfiguration scheme; interconnection phase; processor arrays; redundancy; Algorithm design and analysis; Area measurement; Circuit faults; Computer architecture; Hardware; Integrated circuit interconnections; Logic arrays; Redundancy; Time measurement; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Application Specific Array Processors, 1990. Proceedings of the International Conference on

Conference_Location

Princeton, NJ

Print_ISBN

0-8186-9089-5

Type

conf

DOI

10.1109/ASAP.1990.145470

Filename

145470